Floating gate transistors are widely used in semiconductor manufacturing because of their ability to store charge in the floating gate disposed between lower and upper dielectrics formed beneath the gate electrode. Floating gate transistors are used to form flash memory cell structures such as discussed in K. Kim and G. Koh, “Future Memory Technology Including Emerging New Memories”, Intl. Conf. on Microelectronics, p. 377-384, 2004, and G. Atwood, “Future Directions and Challenges for ETox™ Flash Memory Scaling”, IEEE Trans. Device and Materials Reliability vol. 4, no. 3, September 2004. Such cell structures typically use a dual-poly floating gate structure with the polysilicon floating gate serving as a charge storage medium as shown in FIGS. 1A-1C. The tunnel-oxide of such devices is usually 90 angstroms—110 angstroms and the inter-poly or upper dielectric is usually a composite of ONO (Oxide-Nitride-Oxide) with an equivalent oxide thickness of about 200 angstroms to about 300 angstroms, roughly 2× or 3× the tunnel-oxide thickness. The thickness of the tunnel-oxide and upper dielectric are determined by the stringent retention requirements of retaining charge for greater than ten years at 125° C.
Programming of the floating gate flash memory cells is typically performed by channel hot electron (CHE) injection or channel F-N (Fowler-Nordheim) tunneling. Erasure of the cell is typically accomplished by F-N tunneling through the tunnel-oxide and into the channel. The cell may be an ETox™ cell based on either NMOS or PMOS transistors with floating gate storage of electrons or holes respectively. The channel current during the read operation is modulated by the amount of charge stored on the floating gate representing logic states “1” or “0”. The amount of stored charge is limited by the material used for the floating gate which is typically a single polysilicon layer.
FIGS. 1A-1C illustrate a typical conventional floating gate transistor 100 that includes gate structure 102 formed over channel 104 formed in a substrate. Channel 104 is between source and drain regions 108. Gate structure 102 includes lower tunnel-oxide 110 and upper dielectric 112, described above, along with floating gate 114 and gate electrode 116. In such conventional floating gate transistors, each of gate electrode 116 and floating gate 114 are formed of a single layer of polycrystalline silicon. The exemplary floating gate transistor may be an ETox™ cell that includes p-well 122, n-well 124 and p-type substrate 126. FIGS. 1A-1C illustrate the exemplary floating gate transistor 100 in read, program, and erase operations, respectively. Charge is indicated by electrons 130.
The conventional technology is limited by the ability of the floating polysilicon gate to store charge. The minimum thickness of the tunnel-oxide in upper dielectrics is determined by the stringent requirement of charge retention for greater than ten years at 125° C. Once the thickness of these dielectric materials is determined, the cell size is then set by the required coupling ratio (typically about 0.8). Often the floating gate cell would benefit from increased area to accommodate larger capacitance coupling between the floating gate polysilicon and the control gate. An increase in device area is obviously is quite undesirable as the drive to increase integration levels mandates increasingly smaller features of smaller area.
As such, there is a need for better charge retention which will enable both the tunnel-oxide and the upper dielectric to be further scaled down without a trade-off to the retention performance or requiring an increase in size/area. Improved charge retention would enable the desirable result of further scaling down the cell size and also reducing the program/erase operating voltage accordingly. The present invention addresses these shortcomings and provides a floating gate with superior charge retention characteristics.